Modern integrated circuits (ICs) are fabricated in a planar fashion using “top-down” processes, where the reaction species is directed downward onto a substrate surface in a direction normal to the semiconductor substrate. During a conventional etching process, for example, a plasma is used to accelerate etchant species ions toward the substrate, where the ions are used to etch away unwanted material. The bulk of the etchant acceleration occurs in a “plasma sheath”, the shape of which is determined by the etch chamber geometry and the local topography of the substrate.
To facilitate increased integration and speed of semiconductor devices, a geometrical progression of continuously scaling semiconductor devices (e.g., decreasing transistor size, increasing transistor density, etc.) has emerged. Reducing the size of a semiconductor device and/or a feature size of a semiconductor device can provide improved speed, performance, density, cost per unit, etc., of resultant integrated circuits. However, as the size of semiconductor devices and device features have been reduced, the planar type of fabrication techniques mentioned above are being challenged in their ability to produce modules comprising a plurality of integrated circuits located with high proximity to each other. For example, field effect transistors (FETs) are currently being fabricated with a gate feature that is only 22 nm wide—which is only a few tens of atoms in total. Clearly, the limits of lateral scaling of devices, and their manufacture, are being reached. Accordingly, the Semiconductor Industry Association has recognized the limits of conventional planar manufacture of semiconductor devices and has identified three-dimensional integrated circuit (3D-IC) fabrication as a core enabler in keeping pace with Moore's Law.
While various integrated circuits currently being manufactured are referred to as “three dimensional”, they are truly formed of a multiple number of planar (i.e., two-dimensional) layers that are stacked one on top of another. As such, these circuits are fabricated using standard top-down planar process flow techniques, with through-wafer vias used to attach components on different layers to each other. Alternatively, wafer-to-wafer bonding may be used (in a face-to-face configuration) to provide electrical and/or optical connections between elements on adjacent planar structures.
The conventional processes used to form these multi-layer stacks cannot, however, be extended to perform process steps on the “vertical” walls of a structure, which is required to capture 3D volumetric scaling of transistor density. Therefore, in order to enable true 3D-IC fabrication, where the functional semiconductor devices are fabricated on surfaces which are not parallel to the wafer surface, new approaches to semiconductor device manufactured have to be engendered.
A new fabrication method for creating features on interior sidewalls of 3D semiconductor structures is described in detail in U.S. Pat. No. 8,197,887, issued on Jun. 12, 2012 and assigned to the assignee of this application. Here, a membrane exhibiting a pre-defined pattern is placed over an opening (cavity) of an individual die (referred to as a “unit cell”). A source of etchant (or material to be deposited) is oriented at a defined angle with respect to the unit cell, with the reactant species passing through the patterned membrane at an angle other than 90°, allowing for the pattern (etched or deposited material) to be re-created on a vertical sidewall of the unit cell. By moving the source into different orientations with respect to the unit cell, patterning of all interior sidewalls may be obtained.